Forgeout takes a spec or a netlist, finds a smaller and shallower version, proves it computes the same function, and hands you the tape-out calldata for X Layer.
Exact synthesis up to three inputs, plus rewriting for larger functions (ABC also runs in the CLI, not in this browser build). Pick area, depth, or balanced, and aim at a reference cost.
Every result is checked against the original, exhaustively up to 20 inputs and by SAT beyond that. A second, separate tool re-checks the published circuits.
Copy the netlist or the ready-made tape-out calldata, send it from your own wallet, and list the circuit in the registry (live on X Layer).
Runs in your browser. Nothing is uploaded.
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q = reference C ÷ our C, capped at 4. C = area × depth³ with two output buffers per output counted. Costs are never converted into reward amounts.
Measured on an X Layer fork. The block gas limit is 210,000,000, so six inputs fit with room to spare.
| Inputs | Rows checked | Gas |
|---|---|---|
| 3 | 8 | 342,856 |
| 4 | 16 | 690,567 |
| 5 | 32 | 2,190,727 |
| 6 | 64 | 7,556,637 |
Forgeout exports a checked circuit as a Tiny Tapeout project: structural Verilog, the template wrapper, and the GitHub Actions flow that produces the layout. A majority-of-three test circuit has already gone through that open-source flow (davieslennox0/maj3-silicon-spike).
Forgeout stops at Exported. The last two steps belong to the circuit owner.
failure because four unrelated checks fail on the generated repo: viewer (Pages not enabled), gl_test and the separate test workflow (no cocotb testbench written for this design), and the docs workflow (template placeholder in docs/info.md). The gds and precheck jobs this claim depends on both passed for real. See run 40368814040.Tapeout-ready export. We have not ordered fabrication. Ordering is a separate paid step that the circuit owner completes on Tiny Tapeout. We do not claim a physical chip exists.
The numbers above are what was measured. These are the edges of them.
FabX does not publish all of its reward variables, so Forgeout reports cost C and score q only, never a payout.
The other 54, including every sequential task, ship only sampled test vectors. Fitting those would be overfitting, so they are left out.
Exact synthesis is proven only up to three inputs. Above that Forgeout is heuristic and sometimes loses.
The first registry (v1) has six entries registered at depth 0 before a fix; it is immutable and prices depth 0 as 1, so those entries misprice its best-circuit comparison. The five showcase circuits were re-registered in v2 with real depths. The registry takes gates and depth from the caller without checking them, and “verified on-chain via processor.eval” means the supplied outputs matched the processor’s own eval of that circuit, not the task specification.
We have not ordered fabrication; that is a separate paid step the circuit owner takes. On this page, tape-out means the on-chain TapeOut circuit unless it says silicon.